Course code UPM56
Course title Fundamentals of VHDL & SystemC
Institution Universidad Politecnica de Madrid
Course address EUITT. Ctra. Valencia, Km.7 28031 Madrid
City Madrid
Minimum year of study 3rd year
Minimum level of English Good
Minimum level of French None
Key words Digital Design, HDL, FPGA, C++/C language
Language English
Professor responsible Eduardo Juárez
Telephone +34 91 336 5531
Fax +34 91 336 7801
Email ejuarez@euitt.upm.es
Participating professors César Sanz
Number of places Minimum: 10, Maximum: 16, Reserved for local students: 8
Objectives
  • To be familiar with programmable logic devices.
  • To learn VHDL enough to be able to build synthesizable descriptions of combinational and sequential circuits as well as structural. To learn the basics of the language.
  • To be able to build testbenches and run VHDL simulations.
§         To use simulation and synthesis CAE tools.§         To learn the basics of the SystemC language to be able to build system functional models
Programme to be followed 1.- Programmable Logic Devices: Introduction, Programmable Logic Devices taxonomy2.- VHDL Language : Designing with Hardware Description Languages (HDL), VHDL language basics, Examples3.- SystemC Language: Modules, Interfaces, Channel Fundamentals, ProcessesLab. 1: VHDL Modelling and SimulationLab. 2: Hardware prototypingLab. 3: SystemC Modelling and Simulation
Prerequisites §         Digital electronics (more than fundamentals)§         CAD tools §         C programming language
Course exam
  • Questionnaire
  • Labs.
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